As semiconductor devices shrink to smaller dimensions, device speeds increase and substrate capacitance effects become an increasingly large contributor to device cycle times. This problem is typically addressed by building “silicon on insulator” (SOI) devices, where a thin (˜200 nm), single crystal Si device layer containing the devices is situated on an insulating substrate layer or substrate instead of directly on Si. It should be noted that for the purposes of this invention, we use the term “device layer” to refer to the (nominally) single crystal semiconductor layer in which devices may be built, and that at different times during processing a given device layer may or may not actually have devices in it.
While semiconductor device layers can be grown epitaxially on single-crystal insulating substrates, “Silicon On Sapphire” (SOS) being a prime example, semiconductor device layers are more typically formed in a Buried OXide (BOX) geometry, in which an amorphous oxide (typically SiO2) is sandwiched between a thin semiconductor device layer and a Si wafer substrate. BOX geometry wafers may be produced by “Separation by IMplantation of OXygen” (SIMOX), where a buried SiOx layer is formed by ion implantation of oxygen, and the device layer through which the ions have passed is repaired by a recrystallization anneal.
BOX approaches also include several wafer bonding techniques. In conventional bonding terminology, which we will use here, an epitaxial device layer is grown on a sacrificial “seed wafer.” The device layer is then detached from the seed wafer after it is bonded to a “handle wafer” which will accompany the device layer through the processing steps needed to fabricate the devices. Bonding techniques for BOX SOI include (i) Smart-Cut® (where H implants are used to separate the device layer from the seed wafer after the device layer is bonded to a surface oxide on the handle wafer), (ii) BESOI (“Bond-Etchback SOI,” where the seed wafer is removed by etching after the device layer is bonded to an oxide layer on the handle wafer), and (iii) ELTRAN (“Epitaxial Layer TRANsfer,” where the seed wafer contains a porous Si layer on which the device layer is first grown, then partially oxidized, and then finally bonded to the handle wafer, after which the device layer is separated from the seed wafer by a collimated water jet which breaks apart the porous Si layer. These and other wafer bonding methods are described in U.S. Pat. No. 5,710,057, issued Jul. 12, 1996 to D. M. Kenney. Smart-Cut® process is described in U.S. Pat. No. 5,374,564 by M. Bruel which issued Dec. 20, 1994 and in U.S. Pat. No. 5,882,987 by K. V. Srikrishnan which issued Mar. 16, 1999. BESOI SOI is described in U.S. Pat. No. 5,906,951 by Chu et al. which issued May 25, 1999.
However, a problem with using SOI substrate wafers made by these techniques is that the processing to form the devices in the device layer is done after the device layer has been bonded to (or grown on) a handle wafer which also acts as the final substrate for the devices. The handle wafer must thus be able to survive the processing steps required to form the devices (e.g., activation anneals, etc.).
Unfortunately, few wafer substrate materials are sufficiently compatible with the high temperatures and temperature cycling of Si processing. Highly insulating (>1 kΩ-cm) Si wafer substrates are potentially suitable substrates, but they are expensive and easily warped (a problem for lithography) compared to conventional lightly doped (10 to 100 Ω-cm) Si wafers. Sapphire wafer substrates are also expensive, and present concerns about thermal expansion mismatches between Si and sapphire (Al2O3). In addition, the epitaxially-grown Si layers in SOS wafers typically have a high density of defects, due to imperfect lattice matching of the Si and sapphire (Al2O3).
BOX approaches typically use lightly doped Si wafer substrates with a buried SiO2 layer as the insulator. While the Si wafer substrate is completely compatible with Si device processing, the SiO2 layer must be thin, both to reduce thermal mismatch stresses to the Si device layer during processing, and to prevent thermal isolation of the device layer (and device heating) during device operation. BOX approaches using SiO2 as the buried oxide are thus of limited value in spacing apart the device layer from the Si wafer substrate. More thermally conductive materials such as Al2O3, AlN, or diamond may be used as a thicker insulating “BOX” layer, but concerns about thermal expansion mismatches again remain.
These difficulties with building SOI devices on SOI substrate wafers can be circumvented by transferring the device layer to the substrate of choice after the devices have been formed in the device layer. Previous implementations of this approach include (i) U.S. Pat. No. 5,877,034, “Method of making a three-dimensional integrated circuit,” issued Mar. 2, 1999 to Ramm and Buchner, which describes fabricating a device-containing device layer (including optional interconnection layers) on a first substrate, transferring device layer to an auxiliary substrate, removing the first substrate by a “thickness reduction” process comprising polishing or grinding, bonding the device to a final substrate, and, finally, removing the auxiliary substrate, and (ii) U.S. Pat. No. 5,674,758, “Silicon on insulator achieved using electrochemical etching,” issued Oct. 7, 1997 to McCarthy, which describes forming a device-containing device layer on a first substrate, transferring it to a final substrate, and removing the first substrate by standard etching techniques in combination with electrochemical etching techniques. However, these approaches require a sacrificial wafer which cannot be reused, as well as stringent endpoint control to avoid continuing the sacrificial wafer etch into the device layer. The use of a sacrificial release layer between the device-containing device layer and its original substrate allows reuse of the original substrate. This sacrificial release layer approach, exemplified by U.S. Pat. No. 5,528,397, “Single crystal silicon transistors for display panels,” issued Jun. 18, 1996 to Zavracky et al., typically requires a thermally stable release layer (e.g., SiO2), and the use of channels or grooves in the device layer to provide a path for the etchant to reach and dissolve away the release layer. However, the need for grooves, and concerns about device damage from the release layer etchant are disadvantages of this approach. It would therefore be desirable to have an improved method for transferring device-containing device layers from one substrate to another.
BOX approaches to forming SOI wafer substrates that are based on bonding a semiconductor device layer to a handle wafer require a method for separating a semiconductor layer from the seed wafer substrate. In the prior art ELTRAN process, separation is accomplished by breaking apart a porous layer which initially connects the semiconductor layer to the seed wafer substrate. A schematic of the ELTRAN process based on the description of K. Sakaguchi and T. Yonehara in Solid State Technology, June 2000, p. 88 is shown in FIGS. 1A–1G. FIG. 1A shows silicon seed wafer 10 after formation of porous silicon layer 20. A high-quality epitaxial Si layer 30 (the device layer) is then grown on porous silicon layer 20 to form the structure of FIG. 1B. A portion of silicon layer 30 is then thermally oxidized to form thermal oxide layer 40 shown in FIG. 1C. The structure of FIG. 1C is then bonded to Si handle wafer 50 to form the 2-wafer structure of FIG. 1D. Porous Si layer 20 is then split by a pressurized water jet 60, as shown in FIG. 1E, to form the structure of FIG. 1F with handle wafer 50, thermal oxide layer 40, device layer 30, and residual porous Si layer 20′. FIG. 1G shows the final SOI structure obtained after removing residual porous Si layer 20′, and etching/annealing the device layer to make it smooth and flat.
While this traditional ELTRAN approach to forming SOI wafer substrates has been successfully demonstrated, several aspects are open to improvement. To ensure a porous silicon layer that can be cleanly broken, ELTRAN typically employs a double layer of porous silicon comprising a first porous Si layer with a first porosity, and a second porous Si layer with a different porosity. High stress concentrations are present at the interface between the two porous Si layers, an arrangement that facilitates wafer splitting, since wafer splitting will relieve the stress. However, it can be difficult to engineer the appropriate stress differentials so that the porous silicon is weak enough to split with the water jet yet strong enough to survive processing. It would be desirable to have another method of designing porous Si-based layers that can be easily and controllably split apart. Another concern with the traditional ELTRAN approach is water jet alignment; careful alignment is needed to ensure that the water jet impinges only on the porous silicon layer and does not attack the device layer or seed wafer surface. It would be desirable to have a splitting process that does not require any alignment.
In view of the above-described circumstances it is therefore an object of this invention to provide an improved method for forming structures comprising thin device-containing device layers on insulating or specialty substrates selectable without regard to the substrate's compatibility with silicon processing.
It is a further object of this invention to provide a thin device-containing device layer on an insulating or specialty substrate for use as an integrated multifunctional system-on-a-chip.
It is an additional object of this invention to provide an alternative to the ELTRAN method for separating a semiconductor layer from a substrate, and more particularly to improved methods for forming and splitting or breaking apart the porous layer by which the semiconductor layer and substrate are initially joined or connected.